Testability of Sequential Circuits with Multi-Cycle False Path

This paper investigates the relationship between multi-cycle false paths and the testability of sequential circuits. We show that removal of multi-cycle false paths (either by circuit restructuring or by proper state encoding) improves circuit testability, but not as signiicantly as one would expect. We demonstrate the inability of current structure-based scan register selection techniques to select the minimum possible set of registers for high fault coverage. We then propose a novel and eecient way to exploit the causes of multi-cycle false paths to make a judicious choice of registers for maximum possible testability. Our technique is based on the analysis of the circuit behaviour and its state encoding. It is shown that this approach results in the selection of minumum possible scan register set for maximum possible fault coverage.